1. Field
One or more embodiments of the invention relate to the field of manufacturing integrated circuits. In particular, one or more embodiments of the invention relate to the field of polishing wafers.
2. Background Information
Polishing is a well-known process that is commonly used in the manufacture of microprocessors and other integrated circuits. The polishing may be used to remove material from the surface of a wafer or other substrate in order to reduce roughness, planarize the surface, and/or reduce the thickness of the substrate. A common type of polishing presently in widespread use is chemical mechanical polishing (CMP) in which a reactive slurry having a liquid and an abrasive is used for polishing.
It is often proves challenging to consistently control polishing in integrated circuit manufacturing processes. There are various reasons why this may be the case.
One potential reason is that the polishing rate may tend to change or drift over time do to degradation or other modification of the abrasive or other polishing material. As a result, wafers polished at different times in the abrasive lifecycle may experience different polishing rates.
Another potential reason is that the different polishing heads on a polishing tool, and/or among different polishing tools, may have different polishing rates. As a result, wafers polished with different heads and/or tools may experience different polish rates.
Yet another potential reason is that the pre-polish thickness of layers of the starting wafers that are input to the polishing process may vary over time due to variability in material deposition processes that are encountered prior to the polishing process. As a result, wafers polished at different times in the integrated circuit manufacturing process may need different amounts of polishing to achieve the same final thickness.
Each of these sources of variability may tend to lead to variability in the post-polish thickness of layers of the polished wafers if efforts are not taken to control the affect of these variations on the-polishing process. Such variability is generally undesirable.
One prior approach to attempt to control the affect of variation in the thickness of the polished wafers is to use test wafers to determine an appropriate polish time for a polishing tool prior to polishing a wafer lot with the polishing tool. However, there are a number of potential drawbacks to this approach.
One potential drawback is the cost of using dedicated test wafers to calibrate the polishing process. Another potential drawback is the downtime of the polishing process while the test wafers are being polished to determine the appropriate polish time. Yet another potential drawback is the time and cost to use technicians to make decisions about the appropriate polish time for each wafer lot based on the polishing of the test wafers. A further potential drawback is that due, at least in part, to the drawbacks described above, all of the multiple different polishing heads are typically not tested separately with dedicated test wafers. Instead a single polishing time is generally used to represent multiple different polishing heads. This may not adequately take into account head-to-head variation in polishing rates.